The present invention relates to a bus arbitration means mounted in various information processors such as a personal computer and work station and more particularly to a means for performing suitable arbitration by improving the bus access efficiency when accesses to an I/O device and a storage compete each other.
As a bus installed in various conventional information processors which is a high-speed system bus in view of multi-processor control, for example, the so-called xe2x80x9cFuture bus+xe2x80x9d described in xe2x80x9cIEEE Draft Standard P896.1 R/D8.5: Future bus+ Logical Layer Specifications, IEEE Computer Society Press (1991) PP 63-104xe2x80x9d has been proposed.
With respect to a high-speed information processor such as a server comprising a personal computer or work station, there are many processors having a structure using a high-speed system bus represented by such Future bus+. To such a system bus, a plurality of modules, for example, a plurality of processors, a processor interface, a main storage, an I/O device, and others are connected. With respect to an I/O device, a constitution that the I/O device is connected to a system bus via a converter for performing protocol conversion of information on the system bus to information on an I/O bus and the I/O bus is often proposed.
Recently, however, in the field of information processors, as the system clock frequency to be supplied to a processor increases suddenly, it is becoming one of the greatest factors for deciding the system performance whether the data access speed to a processor and main storage can be increased in correspondence with high performance of the processor.
In such a system, a constitution that a bus for connecting a processor and main storage and an I/O bus for connecting an I/O device are individually installed via a bus converter (bus adapter), that is, the so-called hierarchy of buses has advanced in view of compatibility with an existing I/O device, multi-line connection, and connection to various I/O devices.
Therefore, it is important to develop a bus control means for performing various conversion processes between buses efficiently. Furthermore, an art of bus control for realizing a higher throughput is, for example, disclosed in Japanese Laid-Open Patent Application Number 5-324544. In these buses, to realize a high throughput, use of a method that a buffer for transaction reception is provided beforehand in the module on the bus slave (hereinafter referred to as just xe2x80x9cslavexe2x80x9d properly) side without performing handshaking in each cycle and data is continuously written into the buffer installed in the slave on the receiving side after the bus master obtains a bus access has been proposed.
Conventionally on a system bus provided in various information processors, xe2x80x9cmemory accessxe2x80x9d of accessing to a main storage by a processor, xe2x80x9cPIO accessxe2x80x9d of accessing to an I/O device by a processor, and xe2x80x9cinter-processor communicationxe2x80x9d for controlling so as to match cache storage contents are mainly executed frequently.
On the other hand, access to an I/O device is executed at a comparatively low speed, so that a method that a dedicated I/O bus is installed and the I/O bus is hierarchically connected via a bus converter is generally used. In this case, the I/O bus operates generally at a speed lower than that of the system bus to which the processor and main storage are connected, so that there is a problem imposed that the access to the main storage by the processor and the inter-processor communication are made wait by the PIO access and the bus access efficiency reduces.
The following may be considered as a reason for it.
When PIO access is continuously generated from a certain processor or a plurality of processors, an I/O bus connected via a bus converter operates generally at a low speed, so that there is a possibility that the next PIO access is generated from the processor side before the process for access data of the PIO access collected in a buffer (PIO buffer) installed in the bus converter ends. However, if there is no empty area in the PIO buffer, the buffer cannot receive access data for the next PIO access request.
In this case, if the bus system is not structured so that a retry protocol, that is, xe2x80x9csince PIO access cannot be received, a request of retryxe2x80x9d is issued from the slave side to the master side and further xe2x80x9ca transfer instruction which is an object of retry request is executed again after a predetermined timexe2x80x9d by the master side, the access request will be lost.
It also can be considered to deal with it by executing control of granting no bus access to a module other than the bus converter by the bus arbiter until an empty area is generated in the PIO buffer. In this case, however, a problem arises that even if access to the main storage and inter-processor communication are requested from a processor other than the processor issuing the PIO access request, they cannot be executed.
Even if the retry protocol is supported by the system bus, many unacceptable retry transfers are generated, so that a problem inevitably arises that the bus access efficiency reduces.
As a background of occurrence of such problems, existence of a need for making a multiprocessor system cheaper may be cited. Namely, although the multi-processor system is used conventionally in the field of main frames, in an I/O system, a channel connected in a one-to-one correspondence is used instead of a bus.
Recently, however, particularly in the field of personal computers, since many buses sharing one transmission line on a time-shared basis are used so as to reduce the price, such a problem is caused. In view of the above problems, an object of the present invention is to provide an information processing system comprising a bus connecting a processor and a bus connecting an I/O device hierarchically, wherein the bus access efficiency is improved by preventing execution of main storage access and inter-processor information transfer from entering a standby state due to PIO access which is a low-speed process.
More concretely, an object of the present invention is to provided system for performing arbitration suitably by improving the bus access efficiency, a bus arbiter used for it, and an arbitration method when accesses to an I/O device and a storage compete each other.
To solve the above problems and accomplish the object of the present invention, the present invention has the following constitution. Namely, the system is a system comprising a. first bus, a second bus operating by a communication protocol different from that of the first bus, a plurality of modules connected to the first and second buses, a bus conversion means for performing at least protocol conversion of information between the two buses, a bus arbiter for arbitrating a bus access request issued by a bus master, and when the access destination of the bus master is a predetermined module, a storage means for storing data specifying the access up to a predetermined amount, wherein among a plurality of modules connected to the first bus, at least two modules are bus masters having a function for outputting access destination information.
The system is an information processing system wherein when the aforementioned bus arbiter judges that one of the bus masters issues a bus request when it performs an access operation, the bus arbiter refers to the access destination information and the data storage status of the storage means and decides whether or not to grant a bus access to the bus master. More concretely, the system is a system wherein when a predetermined amount of information is stored in the storage area of the storage means, the bus arbiter refers to the access destination information outputted by the bus master issuing the bus access request and when the bus arbiter judges that the access destination is not the predetermined module where the storage means stores data, the bus arbiter grants a bus access to the bus master of the highest priority order issuing the bus access request and when the bus arbiter judges that the access destination is the predetermined module where the storage means stores data, the bus arbiter grants bus access to the bus mater of the highest priority order issuing the bus access request except the bus mastter outputting the access information.
As a more concrete embodiment, there is a means described below. the storage means stores data, the bus arbiter the bus master of the highest Namely, the modules connected to the first bus contain at least one processor, a processor interface for at least two processors, and a memory interface connected to a storage, and a module to be a bus master has a priority order for granting a bus access, and when the modules to be connected to the second bus are at least one I/O means and the access destination of the bus master is one I/O means, the storage means can store data for specifying the access up to a predetermined amount.
The system is a system wherein when a predetermined amount of information is stored in the storage area of the storage means and the processors and processor interfaces issue a bus access request as a bus master, the bus arbiter refers to the access destination information outputted by the bus master and when the access destination is not one of the I/O means, the bus arbiter grants a bus access to the bus master of the highest priority order and on the other hand, when the access destination is one of the I/O means, the bus arbiter grants a bus access to the bus master of the highest priority order among the bus masters performing an access operation to the memory interface.
According to the aforementioned means, in an information processing system comprising a processor, main storage, and I/O device and having a plurality of kinds of buses, a bus access is arbitrated as described below.
The system has the first bus and the second bus operating by a communication protocol different from that of the first bus and a plurality of modules are connected to the first and second buses. At least two ones among a plurality of modules connected to the first bus are bus masters and the bus masters output access destination information.
The bus conversion means performs at least protocol conversion of information between the first bus and the second bus. When the access destination of a bus master is a predetermined module, the storage means is structured so as to store data for specifying the access up to a predetermined amount.
The bus arbiter performs a process of arbitrating a bus access request issued from a bus master, that is, when the bus arbiter judges that one of the bus masters issues a bus access request when it performs an access operation, the bus arbiter refers to the access destination information and the data storage status of the storage means and decides whether or not to grant a bus access to the bus master.
More concretely, the bus arbiter operates as described below.
Namely, when a predetermined amount of information is stored in the storage area of the storage means, the bus arbiter refers to the access destination information outputted by the bus master issuing the bus access request.
When the bus arbiter judges that the access destination is not the predetermined module where the storage means stores data, the bus arbiter grants a bus access to the bus master of the highest priority order issuing the bus access request. On the other hand, when the bus arbiter judges that the access destination is the predetermined module where the storage means stores data, the bus arbiter operates so as to grant a bus priority order issuing the bus access request except the bus master outputting the access information and arbitrates the bus.
According to a more concrete embodiment of the present invention, the operation thereof is as described below.
Firstly, the modules connected to the first bus contain at least processor interfaces for at least one processor and at least two processors and a memory interface connected to a storage. A module to be a bus master has a priority order for granting a bus access. When the modules to be connected to the second bus are at least one I/O means and the access destination of the bus master is one I/O means, the storage means can store data for specifying the access up to a predetermined amount.
When a predetermined amount of information is stored in the storage area of the storage means and the processors and processor interfaces issue a bus access request as a bus master, the bus arbiter refers to the access destination information outputted by the bus master.
When the access destination is not one of the I/O means, the bus arbiter grants a bus access to the bus master of the highest priority order. On the other hand, when the access destination is one of the I/O means, the bus arbiter performs an information process of granting a bus access to the bus master of highest priority order among the bus masters performing an access operation to the memory interface.
According to the present invention, an access destination of a module requesting a bus access can be grasped before an access operation is performed actually, so that a bus access can be granted to a module performing access to the main storage and inter-processor communication which require high speed priority basis.
Therefore, an occurrence of a situation that execution of a transaction such as access to the main storage and inter-processor communication which require high speed is made wait due to comparatively low speed PIO access can be prevented, so that the bus access efficiency is improved. Even if the retry protocol is supported by the system bus, the number of retry transfers contributing to no data transfer can be reduced, so that the bus access efficiency is improved.